EDN

SPICE-based stochastic design of SRAM Array considering PVT variations

Seeking an internship position during the summer of 2011 in the area of Digital ASIC Design with focus on Front-end design, Verification or Layout. Obtained Bachelor’s degree in Electronics ...
Electronic Design

Should Dual Rail Go Mainstream in Deep Nanometer Era?

Deep sub-nanometer designs are stressed with large process variability. SRAM-bits have the most aggressive design rules in the SoCs, and the most variability. A dual rail solution offsets some of the ...
Design-Reuse

A 55-nm Ultra Low Leakage SRAM Compiler with Optimized Power Gating Design

In this paper an optimized power gating design on a 55-nm Static Random Access Memory (SRAM) compiler is presented. Two low leakage modes: retention and sleep mode are discussed. The arrangement of ...
EDN

MEMORIES: 1T SRAM for the masses

Fremont, Calif. — Even as design reuse evolves, taking much of the pain out of system-on-chip design for smaller design teams, embedded memory remains a problem. There are competent SRAM compilers for ...
Semiconductor Engineering

Computational SRAM (C-SRAM) Solution Combining In- and Near-Memory Computing Approaches

New academic paper titled “Towards a Truly Integrated Vector Processing Unit for Memory-bound Applications Based on a Cost-competitive Computational SRAM Design Solution”, from researchers at Univ.